| EU RoHS |
Not Compliant |
| ECCN (US) |
3A001a.7.a. |
| Part Status |
Obsolete |
| HTS |
EA |
| SVHC |
Yes |
| SVHC Exceeds Threshold |
Yes |
| Automotive |
No |
| PPAP |
No |
| Family Name |
Stratix® II |
| Process Technology |
90nm |
| User I/Os |
742 |
| Number of I/O Banks |
8 |
| Operating Supply Voltage (V) |
1.2 |
| Shift Registers |
Utilize Memory |
| Logic Elements |
132540 |
| Number of Multipliers |
252 (18×18) |
| Program Memory Type |
SRAM |
| Embedded Memory (Kbit) |
6589.7 |
| Total Number of Block RAM |
6+609+699 |
| IP Core |
Viterbi Compiler, High-Speed Parallel Decoder|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Provider Name |
Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA |
| Device Logic Units |
132540 |
| Number of Global Clocks |
16 |
| Device Number of DLLs/PLLs |
12 |
| Dedicated DSP |
63 |
| Programmability |
No |
| Reprogrammability Support |
No |
| Copy Protection |
No |
| Opr. Frequency (MHz) |
609.76 |
| In-System Programmability |
Yes |
| Speed Grade |
5 |
| GMACs |
66.15 |
| Mega Multiply Accumulates per second |
66150 |
| Differential I/O Standards |
LVPECL|LVDS |
| Single-Ended I/O Standards |
HSTL|LVTTL|CMOS|SSTL |
| Maximum I/O Performance |
1Gbps |
| External Memory Interface |
RLDRAM II|QDRII+SRAM|DDR SDRAM|DDR2 SDRAM |
| Minimum Operating Supply Voltage (V) |
1.15 |
| Maximum Operating Supply Voltage (V) |
1.25 |
| I/O Voltage (V) |
1.5|1.8|2.5|3.3 |
| Minimum Operating Temperature (°C) |
-40 |
| Maximum Operating Temperature (°C) |
100 |
| Supplier Temperature Grade |
Industrial |
| Tradename |
Stratix |
| Mounting |
Surface Mount |
| Package Height |
3(Max) |
| Package Width |
33 |
| Package Length |
33 |
| PCB changed |
1020 |
| Standard Package Name |
BGA |
| Supplier Package |
FC-FBGA |
| Pin Count |
1020 |
| Lead Shape |
Ball |
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